Title:
処理素子の連鎖を備える電子回路
Document Type and Number:
Japanese Patent JP2007506297
Kind Code:
A
Abstract:
A chain of processing element ( 10 a , 10, 10 b) with a logic circuit ( 14 ) and a storage element ( 12 ) is provided. The storage elements ( 12 ) of all except a final processing element ( 10 b) in the chain have one or more outputs coupled to the logic ( 14 ) of a next processing element ( 10 a , 10, 10 b) in the chain. A timing circuit ( 16 ) controls respective loading time points at which the storage elements ( 12 ) load data from the logic circuits ( 14 ) in respective ones of the processing elements ( 10 a , 10, 10 b). The data is loaded progressively later in processing elements ( 10 a , 10, 10 b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element ( 10 b) includes loading time points of loading all processing elements ( 10 a , 10 ) other than the final processing element ( 10 ).
Inventors:
Peters Adrinus MG
Fan Berkel Cornelis H
De Clerco Marc Nu
Fan Berkel Cornelis H
De Clerco Marc Nu
Application Number:
JP2006525957A
Publication Date:
March 15, 2007
Filing Date:
August 30, 2004
Export Citation:
Assignee:
Koninkuryuke Philips Electronics N.V.
International Classes:
H03K5/15; G06F1/32; G06F9/38; G06F15/78
Domestic Patent References:
| JPH10247394A | 1998-09-14 | |||
| JPS60245311A | 1985-12-05 |
Attorney, Agent or Firm:
Susumu Tsugaru
Akihiko Miyazaki
Fueda Shusen
Akihiko Miyazaki
Fueda Shusen