Title:
電子回路
Document Type and Number:
Japanese Patent JP4193060
Kind Code:
B2
Abstract:
An electronic circuit capable of inhibiting a transmission coil, currently transmitting no signals, from interfering with communication in a case of realizing an inter-board communication by use of an inductive coupling. While a chip is not transmitting, a signal (Tx/bar(Rx)) is low, the output of a NOT (12) is high, the output of a NAND (13) is high, and the output of a NOR (14) is low, with the result that transistors (T3,T4) are turned off, placing a transmission coil (15) in an open state. In this way, the transmission coil (15) is inhibited from interfering with the change of the magnetic field and attenuating the transmitted signals.
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Inventors:
Tadahiro Kuroda
Daisuke Mizoguchi
Noriyuki Miura
Takayasu Sakurai
Hiroshi Kawaguchi
Daisuke Mizoguchi
Noriyuki Miura
Takayasu Sakurai
Hiroshi Kawaguchi
Application Number:
JP2004167694A
Publication Date:
December 10, 2008
Filing Date:
June 04, 2004
Export Citation:
Assignee:
Keio University
International Classes:
H04B5/00; H04B5/02
Domestic Patent References:
| JP10255003A | ||||
| JP11046220A | ||||
| JP9142258A | ||||
| JP3085023A |
Other References:
Daisuke Mizoguchi et.al.,A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS),IEEE International Solid-State Circuits Conference, 2004. Digest of Technical Papers.,米国,IEEE,2004年 2月15日,Vol.1 ,Paper7.6
Kouichi Kanda et.al.,1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme,IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ,米国,IEEE,2003年 2月11日,Vol.1,Paper 10.7
Kouichi Kanda et.al.,1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme,IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ,米国,IEEE,2003年 2月11日,Vol.1,Paper 10.7
Attorney, Agent or Firm:
Kazuo Nakamura