PURPOSE: To increase the maximum action frequency as well as decrease the minimum action frequency by using the push-pull type and also depression-type switch FET, thus increasing the action frequency range of the double-phase clock.

CONSTITUTION: Gates 11W13 are provided immediately before switch transistors 14W16 constituting the shift register, and push-pull type signal inversion amplifiers 14W16 are used. At the same time, the depression-type FET is used for high potential side FET-Q2 and Q4 of the input/output side plus low potential side FET-Q3 of the output side each. Then input signal VIN is supplied to each gate of Q1 and Q3 of the earth potential side, and the collective connection is given to the gates of Q2 and Q4 of the side of power potential VDD plus the source of Q2. Thus output signal VOUT is obtained from the source Q4. Accordingly, the amplitude of the output signal is clamped considerably, thus realizing the acceleration for the gate action.