Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ELECTRONIC CLOCK, EXTERNAL ADJUSTMENT DEVICE AND CONTROL METHOD THEREFOR
Document Type and Number:
Japanese Patent JP2002014181
Kind Code:
A
Abstract:

To enhance the operation efficiency of time adjustment of an electronic clock.

An analog electronic clock 10 has a receiving circuit 21 for receiving an adjustment mode release signal of an external adjustment device 30, and a mode control circuit 22. The mode control circuit 22 causes time measurement to take place, when the receiving circuit 21 receives the adjustment mode release signal of the external adjustment device 30.


Inventors:
KAWAGUCHI TAKASHI
FUJISAWA TERUHIKO
MIYAHARA FUMIAKI
Application Number:
JP2000199705A
Publication Date:
January 18, 2002
Filing Date:
June 30, 2000
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SEIKO EPSON CORP
International Classes:
G04C9/00; G04D7/00; G04G21/04; G04R40/00; G04R60/02; (IPC1-7): G04D7/00; G04C9/00
Domestic Patent References:
JPS62135791A1987-06-18
JPS54674A1979-01-06
JPS6015584A1985-01-26
JPH06235778A1994-08-23
JPH1184028A1999-03-26
JPS4725573Y11972-08-09
JPH11183666A1999-07-09
Attorney, Agent or Firm:
River Saki Kenji