PURPOSE: To prevent unnecessary power consumption by achieving a time correction with a fast sending correction signal until a clear in stop time counting circuit in clock is detected.

CONSTITUTION: When a pulse drive switch 10 is opened, an output from an inverter 11 becomes a low level, AND gates 8 and 9 are opened, and a driving pulse from a demultiplier 2 is not charged into a pulse motor 6. At time, an output from an inverter 12 becomes a high level, AND gate 13 is opened, and a stopping time is stored by up counting the driving pulse with a stop time counting circuit 4. When a switch 14 is opened at necessary, the output from the inverter 11 is turned to a high level, the AND gates 8 and 9 are opened, and the circuit 4 does the down counting along with driving the motor 6 by a fast driving pulse from the circuit 2. Then, when the circuit 4 is cleared, the gate 9 is closed by an inversed pulse due to detection of the clear in a clear detection circuit 3, and the fast driving pulse for the motor 6 is stopped. Accordingly, the unncessary power consumption at unported is prevented.