PURPOSE: To avoid defective transfer by changing a frequency of an interrupt signal so as to eliminate a difference between a count of data quantity obtained by a data input output means and a count of occurrences of an interrupt signal generated by a clock count means.

CONSTITUTION: When a CPU 5 is started by an interrupt signal, the number of blocks received at present in the CPU 5, that is, the value of a registor A and the value of a register B representing the count of occurrences of interrupt signals are compared. As the result of comparison, the CPU 5 allows a register C to count a difference between the former and the latter and to accumulate the counts. Then the CPU 5 checks the value of the register C for each prescribed time and when the value is close to '0', it is regarded that a master device is synchronized with a slave device. On the other hand, when the value of the register C is negative, it is judged that the internal clock period is decreased and that the frequency division ratio N of a programmable frequency divider 12 is decreased. Conversely, when the value of the register C is positive, the frequency division ratio N of the frequency divider 12 is too large.