Title:
コンデンサが集積された電子パッケージ
Document Type and Number:
Japanese Patent JP4878100
Kind Code:
B2
Abstract:
Generally provided is a circuit assembly construction for controlling impedance in an electronic package. A large scale, parallel-plate capacitor includes two electrodes separated by a dielectric material. The electrodes serve as reference voltage planes for the electronic package. At least one of the electrodes is patterned such that both electrodes are accessible from a common side of the capacitor. The capacitor is positioned with a first electrode mounted adjacent to an interconnect circuit portion of the electronic package. An electronic device portion of the electronic package is electrically connected, directly or indirectly, to one or more of the electrodes of the capacitor.
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Inventors:
John Di Geisinger
Paul M Harvey
Robert Earl Kushku
Paul M Harvey
Robert Earl Kushku
Application Number:
JP2001555112A
Publication Date:
February 15, 2012
Filing Date:
May 25, 2000
Export Citation:
Assignee:
3M INNOVATIVE PROPERTIES COMPANY
International Classes:
H01L23/12; H01L23/498; H01L23/50; H01L23/64
Domestic Patent References:
| JPH09148746A | 1997-06-06 | |||
| JPH1126943A | 1999-01-29 |
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Aoyama Aoi
Akira Ito
Mitsuo Tanaka
Aoyama Aoi
Akira Ito