PURPOSE: To make it possible to increment the display correcting speed stepwise by selecting a correcting clock based on the combination of a plurality of switching signals.

CONSTITUTION: Based on the operations of a plurality of, e.g., two correcting switches, the levels of switching signals m and n become high or low, and the levels of the outputs from D type FFs 1 and 2 are set high or low. One of AND gates 10W 12 is selectively opened based on the combination of the signals m and n via AND gates 6W8, an inverter 9, and the like. Thus, one of correcting pulses x, y, and z of the frequency divided pulses, whose periods are diferent in stepwise, is outputted, and the display is corrected. Therefore the display correcting speed can be incremented stepwise.