Title:
半導体装置の静電気放電保護
Document Type and Number:
Japanese Patent JP5188017
Kind Code:
B2
Abstract:
An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.
Inventors:
Dipunker Butter Charya
John Sea.Clitz
Bernard El. Morris
Evuda smooth
John Sea.Clitz
Bernard El. Morris
Evuda smooth
Application Number:
JP2005313643A
Publication Date:
April 24, 2013
Filing Date:
October 28, 2005
Export Citation:
Assignee:
Agia Systems Incorporated
International Classes:
H01L21/822; H01L21/8234; H01L27/04; H01L27/088; H03K19/003
Domestic Patent References:
| JP2006019629A | ||||
| JP2002270774A | ||||
| JP2002231886A | ||||
| JP2004087765A |
Attorney, Agent or Firm:
Okabe
Masao Okabe
Nobuaki Kato
Shinichi Usui
Takao Ochi
Teruhisa Motomiya
Asahi Shinmitsu
Katsumi Miyama
Masao Okabe
Nobuaki Kato
Shinichi Usui
Takao Ochi
Teruhisa Motomiya
Asahi Shinmitsu
Katsumi Miyama