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Title:
ELECTROSTATIC INDUCTION-TYPE SEMICONDUCTOR LOGICAL CIRCUIT
Document Type and Number:
Japanese Patent JPS5443690
Kind Code:
A
Abstract:

PURPOSE: To form an electrostatic induction-type semiconductor logical operation circuit (SITL) of a high-speed operation by making the base of an injector thin and high-impurity concentration and making the gate of the FET of a driver low- concentration.

CONSTITUTION: In a junction-type npn injector, n type layer 16 and p+ type injection layer 17 are diffused from the same window, and n type layer 16 except base 17 of the injector is formed by the difference of the diffusion distance between p type and n type impurity. Thus, the thickness of the base layer can be made below 1μm, and current amplification factor α is improved approximately two times as well as a conventional that. Meanwhile, by forming n type layer 16 at a high concentration from n- type epi-layer 2 by diffusion, the extension of a depletion layer from p- type gate layer 4a to p+ type injection layer 17 is restrained to be minute. Therefore, it is sufficient even if the distance from layer 17 to layer 4a is below 1μm. Further, since layer 4a has a low concentration, the capacity between layers 4a and 2 and the capacity between 4a and 5 are lower than conventional those. Thus, an SITL for high-speed operation is formed.


Inventors:
MURAKAMI KENJI
Application Number:
JP11066577A
Publication Date:
April 06, 1979
Filing Date:
September 13, 1977
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L29/80; H01L21/8222; H01L27/02; H01L27/06; H03K19/094; (IPC1-7): H01L27/04; H01L29/76; H03K19/08