Title:
ELEMENT ISOLATING METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS60109246
Kind Code:
A
Abstract:
PURPOSE:To enable to make elements fine and to increase the integration by reduction in the amount of intrusion to element regions by inhibition of the generation of bird beaks by a method wherein the oxidation-resistant film is formed by annealing at high temperature after the first thin oxide film is formed on a semiconductor substrate, and thermal oxidation is performed by selective removal of the former film. CONSTITUTION:The first oxide film 6 is formed on the Si substrate 5 by thermal oxidation. Thereafter, it is annealed in 1,000 deg.C ammonia gas or ammonia plasma. This annealing is desired to be carried out in higher temperatures; however, 600-1,200 deg.C is used. The first oxide film is made dense and strengthens in oxidation resistance by this annealing. Thereafter, an nitride film is formed as the first oxidation-resistant film 7. It is dry-etched in such a manner that the nitride film the first oxidation resistant film 7 is left only in the element-forming region. Next, the first oxide film 6 on the base is wet-etched or dry-etched. This time etching of the first oxide film 6 may be omitted. Then, the process of thermal oxidation is performed.
Inventors:
SUGANUMA TOORU
Application Number:
JP21732483A
Publication Date:
June 14, 1985
Filing Date:
November 18, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/76; H01L21/316; H01L21/762; (IPC1-7): H01L21/95
Attorney, Agent or Firm:
Uchihara Shin