Title:
EMBEDDED TYPE BIT-LINE SOURCE SIDE INFUSION SYSTEM FLASH MEMORY CELL AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3442095
Kind Code:
B2
Abstract:
PURPOSE: To enable contacts commonly used by a large number of cells and to minimize a size of a chip by forming in a method, which has an advantage of source side infusion and can be used in an ideal ground embedded type bit- line array layout.
CONSTITUTION: A floating gate 14, made of polycrystalline silicon is formed on a tunnel oxide film 12 which is formed between separating regions of a field oxide film on a substrate and a layer with an oxide film, a nitride film and an oxide film (ONO), is formed thereon. An oxide film 18 is provided on a sidewall of the floating gate 14 and a gate oxide film 16 is formed adjacent on the substrate. After that an N+-drain inclined junction is formed at the drain side on the substrate, and a spacer 20 made of polycrystalline silicon which is relatively junctioned in an X-direction at the periphery of the floating gate 14 by grouping a source 22 and a drain 24 of each cell. After that, a control gate 28 is formed on the floating gate 14 and the spacer 20 by separating with the ONO and an oxide film 26.
Inventors:
Martin H. Manly
Application Number:
JP26496992A
Publication Date:
September 02, 2003
Filing Date:
October 02, 1992
Export Citation:
Assignee:
National Semiconductor Corporation
International Classes:
H01L21/74; H01L21/8247; H01L23/528; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115
Domestic Patent References:
| JP1304784A |
Attorney, Agent or Firm:
Kaoru Furuya (2 outside)