PURPOSE: To simplify the configuration of the decoder.

CONSTITUTION: A short duration sequence RPS is inputted, a nonsignal term longer than 1μS and shorter than 2μS is detected by a gap detection circuit 25, a flip-flop 26 is turned to a reset state with the detection output, a gate 27 is opened and a gate 28 is closed with the Q output. The pulse sequence RPS is inputted, first and second following pulses of a gap TG or SG are passed through the gate 27, and both of these pulses as one pulse, a PPSSP or SYNC is reproduced by a flip-flop 31 and outputted through a gate 32. An 'H' level is read into the flip-flop 26 with the end of the reproduced pulse, the gate 27 is closed, the gate 28 is opened, and the following RPS is converted to the pulse of a duration 250nS by a pulse generation circuit 33 and outputted from the gate 32.