PURPOSE: To enhance the burst error correction performance without increasing the hardware quantity so much by extracting one constituting unit of two error correcting codes constituting a product code at every code group and transmitting the data in unit of code group.

CONSTITUTION: In an external coding circuit 140, information data inputted from a special reuse interleave circuit 101 is inputted in parallel to a delay circuit 102, P0 parity calculating circuit 110, P1 parity calculating circuit 120, and P2 parity calculating circuit 130. Parity calculating circuits 110, 120, and 130 all have a similar circuit configuration, except that each coefficient of the generating matrix in a generating matrix coefficient table 112 is different from another. These 3 circuits calculate 3-word parity inspection words in parallel. Thus, the maximum burst error length that can be corrected by another code is increased plural times, whereas a reqired hardware quantity of the encoder/decoder is not increased so much. Further, as for information data, it is not necessary to change the arrangement of information data, and as long as information data is arranged in a desired order before error correction signalizing, nothing affects the data arrangement.