PURPOSE: To convert to a code which has prevented "0" from continuing, and to send it out, by utilizing exclusive OR of an output of a sum converting circuit, and a clock signal.
CONSTITUTION: A code train (In) of an NRZ code inputted from a transmitting code input terminal 14 by synchronizing with a clock signal of a frequency f0 is inputted to one input of an exclusive OR circuit 15, a signal which has delayed an output of the exclusive OR circuit 15 by a one bit period by a one bit delaying circuit 16 is inputted to the other input, a sum converting output signal Sn is obtained, this signal and a clock signal C of the frequency f0 and 50% duty ratio is inputted to an exclusive OR circuit 18, and a transmitting output signal is obtained. A decoder is constituted of an exclusive OR circuit and a difference converting circuit.
YAMADA JIYUNICHI
KITSUKAI NORIAKI
