ENCODING AND DECODING FREQUENCY SYNCHRONIZING METHOD

Japanese Patent JP2964899

B2

PURPOSE: To provide encoding/decoding frequency synchronizing method by which the frequencies of an encoding device-side and a decoding device-side can be synchronized with the constitution of a small scale.
CONSTITUTION: A clock generator 4 generates a sampling clock synchronized with a transmission clock and a video reference generator 5 generates a video reference signal synchronized with the sampling clock. A signal source 1 outputs a video signal synchronized with the video reference signal. A highly efficient encoder 6 encodes data based on the sampling clock. A demodulator 11 demodulates a modulation wave and demodulates a transmission clock. A frame synchronizer 15 writes a digital video signal from a highly efficient demodulator 14 based on the sampling clock synchronized with the transmission clock from a clock generator 13, and reads it out, based on the read-out clock of a frequency identical to that of the sampling clock generated by a read clock generator 16.

JP3065948	[Name of device] PLL circuit
JP3000360	[Name of invention] Reference signal generation circuit for communication equipment
JP6664438	Equipment and methods for clock synchronization and frequency conversion

Yoshikawa Wataru

JP3963495A

October 18, 1999

February 28, 1995

Click for automatic bibliography generation  

NEC

H03L7/22; H03M5/12; H04L7/00; H04L7/033; H04L27/00; H04N5/00; H04N7/56; (IPC1-7): H04L7/033; H03L7/22

JP2274032A
JP698196A

Matsuura

Previous Patent: VERTICAL HOLE INSTALLATION STAIRCASE

Next Patent: LEARNING METHOD OF NEURAL NET FOR ASSIGNING CALL