Title:
EPITAXIAL WAFER, AND METHOD OF FABRICATING EPITAXIAL WAFER
Document Type and Number:
Japanese Patent JP2009140965
Kind Code:
A
Abstract:
To provide an epitaxial wafer which is reducible in wafer cracking by using a GaN wafer which is not beveled.
The epitaxial wafer E2 includes the GaN wafer 11 and an InX1AlX2Ga1-X1-X2N (0X11, 0X21, and 0X1+X21) buffer layer 13. A GaN layer 17 is provided between the GaN wafer 11 and InX1AlX2Ga1-X1-X2N buffer layer 13. The GaN layer 17 is grown on a principal surface 11b of the GaN wafer 11. The GaN layer 17 forms a homojunction with the principal surface 11b of the GaN wafer 11. A semiconductor region having optical gain such as an active layer is not provided between the GaN wafer 11 and InX1AlX2Ga1-X1-X2N buffer layer 13. The InX1AlX2Ga1-X1-X2N buffer layer 13 forms a heterojunction 21 with the GaN layer 17.
Inventors:
YOSHIZUMI YUSUKE
UENO MASANORI
UENO MASANORI
Application Number:
JP2007312631A
Publication Date:
June 25, 2009
Filing Date:
December 03, 2007
Export Citation:
Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H01L21/205; C23C16/34; H01L33/06; H01L33/12; H01L33/32
Domestic Patent References:
| JP2002009003A | 2002-01-11 | |||
| JP2003092450A | 2003-03-28 | |||
| JP2005101533A | 2005-04-14 | |||
| JP2002246698A | 2002-08-30 | |||
| JP2005206424A | 2005-08-04 |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Shiro Terasaki
Yoshiki Kuroki
Ichira Kondo
Shiro Terasaki
Yoshiki Kuroki
Ichira Kondo
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