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Patent Searching and Data


Title:
EQUALIZER CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH02166926
Kind Code:
A
Abstract:

PURPOSE: To eliminate the influence of crosstalk on another line by performing equalization control again after decreasing the level of an input signal when the equalization control is not completed in the lapse of prescribed time after detecting a burst signal.

CONSTITUTION: A signal attenuation circuit 21 passes a reception signal (a) as it is as a signal (l) at the beginning and supplies it to a variable gain equalizer 11. In an abnormal case where a crosstalk signal appears as the output (d) of a comparator 2, no reset signal from a burst identification signal generation circuit 15 is outputted, therefore, the overflow of a detecting time monitoring circuit 22 occurs, and a time-over signal (m) is supplied to the signal attenuation circuit 21, and the input signal i attenuated by a prescribed quantity. As a result, the crosstalk signal as the output (d) of the comparator 2 disappears, then, a normal operation can be performed. After the equalization control is applied, the action of the detecting time monitoring circuit 22 is stopped, and real equalization action is performed, and a reproducing signal can be obtained from a comparator 1. In such a way, it is possible to eliminate the influence of the crosstalk on another line.


Inventors:
TAKADA AKIHIKO
Application Number:
JP32230488A
Publication Date:
June 27, 1990
Filing Date:
December 21, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04B3/06; (IPC1-7): H04B3/06
Attorney, Agent or Firm:
Fujishima Ijima (1 outside)