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Patent Searching and Data


Title:
EQUALIZER
Document Type and Number:
Japanese Patent JPS57178412
Kind Code:
A
Abstract:

PURPOSE: To integrate a circuit by giving a next readout number to the 1st memory by loading a value from a stack pointer every time when the 1st address counter counting, and then performing arithmetic at a high speed by performing plural kinds of multiplication simultaneously and successively.

CONSTITUTION: A signal to be equalized from a signal line 100 is converted by an A/D converter 101 into a digital signal, which is stored temporarily in a memory 105 and then transferred to a pipeline type multiplier 107 via a signal line 106. An input signal digitized by said multiplier 107 is multiplied by a coefficient from a coefficient memory 110. The address of the memory 110 is determined by an address counter 114 and the multiplication result of the multiplier 107 is supplied to one input terminal of an adder 118. The output of the adder 118 is fed back to the adder 118 itself to achieve the operation of an accumulator on the whole. Then, an up/down counter 121 is allowed to operate as an accumulator where in the high-order digit bits from the adder 118 are stored, and plural kinds of multiplication are performed simultaneously and successively to perform arithmetic at a high speed.


Inventors:
OOGOSHI MASAE
MASAKI HIROMI
MAEHARA FUMIO
TAKADA YUKIO
Application Number:
JP6379281A
Publication Date:
November 02, 1982
Filing Date:
April 27, 1981
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F7/38; G06F7/508; G06F7/527; G06F17/10; H03H15/00; H03H17/00; H03H21/00; H04B3/04; H04L25/03; (IPC1-7): G06F7/38; H03H17/00



 
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