EQUALIZING CIRCUIT

Title:

EQUALIZING CIRCUIT

Document Type and Number:

Japanese Patent JPH04217113

Kind Code:

A

Abstract:

PURPOSE: To reduce number of parts and to improve feed-through by adapting to connection of plural equalizers to a transmission medium and equalizing the transmission medium to a signal in different data rate. CONSTITUTION: The equalized circuit is provided with the equalizers 40 and 41. Current flows from VCC to a base emitter of Q5 through R7 . Q3 and Q4 form mirror current source for Q1 and Q2 and Q3 and Q4 are interrupted by supplying proper control voltage B1 to bases of Q3 , Q4 , Q5 . When each current source is not interrupted or is not in non-operation state, Q1 , Q2 are operated as a differential amplifier filter with an impedance Z1 and output V out depending on input V in is generated. The equalizer 41 is the same as the equalizer 40, provided with another current source control provided by Q10 and R8 and its impedance Z2 is selected to equalize the transmission medium in different data rate. Switches SW1 and SW2 are controlled by selection signals S1 and S2 and provides bias voltage B1 with Q3-5 and Q8-10 .

Inventors:

JIYON ROTSUKU KUREI
JIERII DAGAA
JIEMUSU UIRIAMU SHIRIBANTO

Application Number:

JP3666691A

Publication Date:

August 07, 1992

Filing Date:

February 07, 1991

Export Citation:

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