Title:
ジッターを低減するべく改良された周波数分割器及びこれに基づく装置
Document Type and Number:
Japanese Patent JP2005508577
Kind Code:
A
Abstract:
A circuit generates an output signal whose frequency is lower than the frequency of an input signal. In an example embodiment, there is a chain of frequency dividing cells. Each of the frequency dividing cells has a pre-defined division ratio and a clock input for receiving an input clock, a divided clock output for providing an output clock to a subsequent frequency dividing cell, a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell, and a mode control output for providing a mode control output signal to a preceding frequency dividing cell. Further included are a latch for altering the division ratio of each of the frequency dividing cells and D-Flip-Flop circuitry having two latches. A first signal clocks the first latch and a second signal clocks the second latch, whereby the frequency of the first signal is lower than the frequency of the second signal.
Inventors:
Zenhua, Wan
Application Number:
JP2002590506A
Publication Date:
March 31, 2005
Filing Date:
May 17, 2002
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H03K23/64; H03K23/66; H03L7/197; (IPC1-7): H03K23/66; H03K23/64
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki