Title:
EQUIPMENT AND METHOD FOR BULK VOLTAGE APPLICATION
Document Type and Number:
Japanese Patent JPH08330927
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To increase operating speed at an activated state and to simultaneously suppress power consumption at an inactivated state for an element with threshold voltage. SOLUTION: Different kinds of bulk voltages are impressed according to the activated and the inactivated operating state of a circuit. For example, if it is a PMOSFET10, the threshold voltage is lowered by impressing an internal power voltage IVCC, and high speed operation is enabled at the activated state of the circuit. The threshold voltage is increased by impressing a higher external power voltage EVCC, and a sub-threshold current is suppressed at the inactivated state of the circuit. A bulk voltage impressing device for this purpose is constituted of PMOSFETs 14, 16 to be complementarily operated by defining a master clock signal ϕC to indicate the operating state of the circuit as a control input.
Inventors:
RI ZAIHIYON
Application Number:
JP12829196A
Publication Date:
December 13, 1996
Filing Date:
May 23, 1996
Export Citation:
Assignee:
SAMSUNG ELECTRONIC
International Classes:
H01L21/8238; G11C11/407; G11C11/408; H01L27/092; H03K17/04; H03K17/687; H03K19/094; (IPC1-7): H03K17/04; H01L21/8238; H01L27/092; H03K17/687; H03K19/094
Attorney, Agent or Firm:
Takeshi Takatsuki