Title:
ディジタル信号受信器におけるタイミング・エラーを推定するよう、訓練列を用いる装置及び方法
Document Type and Number:
Japanese Patent JP2005506799
Kind Code:
A
Abstract:
An apparatus and method is disclosed for estimating timing error in a digital signal receiver from a difference between an arrival time of a first training sequence and an arrival time of a second training sequence in the digital signal receiver. Time domain representations of the timing sequence data are converted into frequency domain representations and used to calculate a complex cross power spectrum. The timing error is obtained by determining an average phase of the complex cross power spectrum. The timing error is then used to calculate an accurate value for the clock rate of the digital signal transmitter.
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Inventors:
Billoo, Doug Nach
Application Number:
JP2003539223A
Publication Date:
March 03, 2005
Filing Date:
October 17, 2002
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H04L7/00; H04L7/027; H04N5/04; H04L7/04; H04N5/44; (IPC1-7): H04L7/00
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito