Title:
ERASING METHOD OF ERASABLE ROM
Document Type and Number:
Japanese Patent JPS5330838
Kind Code:
A
Abstract:
PURPOSE: To erase effectively and accurately in a short time by providing an address designation circuit and a decision circuit at the input side and the output side of a read-only memory respectively.
Inventors:
KISHI TOSHIYUKI
Application Number:
JP10503376A
Publication Date:
March 23, 1978
Filing Date:
September 03, 1976
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G11C17/00; G11C16/02; G11C16/34; (IPC1-7): G11C7/00; G11C17/00
Domestic Patent References:
| JPS52140238A | 1977-11-22 | |||
| JPS5193638A | 1976-08-17 |