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Patent Searching and Data


Title:
ERROR CHECK CODE GENERATING METHOD AND DEVICE
Document Type and Number:
Japanese Patent JPH0993143
Kind Code:
A
Abstract:

To improve the error check capability by receiving ID information as a symbol in the unit of 4-bit and generating a reed Solomon code defined in a finite field GF(24) as an ID information error check code.

The device is made up of a 1st adder 21, a 1st switch 22, a 1st delay device 23, a 2nd adder 24, a 2nd delay device 25, a 1st multiplier 26 multiplying a coefficient of α4, a 2nd multiplier 27 multiplying a coefficient α, and a 2nd switch 28 selecting ID data in 4-bit from the input terminal 20 or 4-bit output data from the 2nd delay device 25 and providing the selected output to an output terminal 29. The delay devices 23, 25 and the multipliers 26, 27 are cleared by a clear pulse ahead the data input. Then the ID information and an error check code for ID information are blocked in the unit of 4-bit and a reed Solomon code defined in a finite field GF (24) based on each symbol is generated as an ID information error check code.


Inventors:
HIGURE SEIJI
OISHI TAKESHI
Application Number:
JP24937995A
Publication Date:
April 04, 1997
Filing Date:
September 27, 1995
Export Citation:
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Assignee:
VICTOR COMPANY OF JAPAN
International Classes:
G06F11/10; G11B20/18; H03M13/00; H03M13/15; H04L1/00; (IPC1-7): H03M13/00; G06F11/10; G11B20/18; H04L1/00
Attorney, Agent or Firm:
Matsuura