Title:
ERROR CORRECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6055737
Kind Code:
A
Abstract:
PURPOSE: To prevent erroneous decision by distinguishing the occurrence of error and the occurrence of disaccord of symbols of a correction block from each other in an error correcting circuit of a cross-interleave BCH code.
CONSTITUTION: If single, double, and triple or multiple disaccords occur in the correction block, disaccord signals L1∼L3 are supplied to l-times, m-time, and n- times continuous detecting circuits 37∼39 respectively. When these detecting circuits 37∼39 detect continuously disaccord signals L1∼L3 l-number of times, m- number of times, and n-number of times respectively, they generate high-level detection signals. When these signals are generated, a deinterleave miss is detected.
Inventors:
NANUN MASAHIDE
KOJIMA TADASHI
INAGAWA JIYUN
KOJIMA TADASHI
INAGAWA JIYUN
Application Number:
JP16367783A
Publication Date:
April 01, 1985
Filing Date:
September 06, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G11B20/18; H03M13/27; (IPC1-7): G11B20/18; H03M13/22
Attorney, Agent or Firm:
Takehiko Suzue