PURPOSE: To select the optimum operation mode in accordance with the using purpose and to lighten the burden of a CPU, by adding operations from the readout of data before correction from a buffer memory to the writing of the data in the buffer memory after correcting the code of the data.
CONSTITUTION: A syndrome register 36, data register 34, majority circuit 41, mode register 80 connected with a timing circuit 27 which designates an operation mode, etc., are provided in an error correcting circuit. Continuous data received by a data receiving circuit 30 are serial-parallel converted at the data register 34 and stored in a buffer memory 29. The data before correction written in the memory 29 are read out and their error is corrected. The corrected data are again written in the memory 29 under the 1st operation mode. Moreover, the data before correction are read out and corrected by means of the registers 34 and 36, circuit 41, etc., and the corrected data are again written in the memory 29 under the 2nd operation mode. Under the 3rd operation mode, data before correction from a CPU are read anc corrected data are sent to the CPU. By selecting two or more operation modes, the burden of the CPU is lightened.
SASE ICHIROU
YANAGIMACHI AKIO
YAMADA TSUKASA
JAPAN BROADCASTING CORP
| JPS5146030A | 1976-04-20 | |||
| JPS4812631A |