ERROR CORRECTION CHECK BITE GENERATOR

Japanese Patent JPS559296

A

The invention concerns a method and apparatus for generating error locating and parity check bytes for a block of data bytes each consisting of k bits. The data bytes are presented in series to a data register (10) and fed in parallel to three channels (21, 22 and 23). Each channel has a random access memory including three registers and a memory address circuit operated, under the control of control means (20), to address the three registers cyclically. The first data byte is combined with the output from the first register of each random access memory, the second data byte with the output from the second register and the third byte with the output from the third register whereupon the cycle is repeated. The result is to generate three parity check bytes in the channel (21), three error locating check bytes in channel (22) and three error locating check bytes in channel (23) corresponding respectively to three interleaved subsets of the block of data bytes. The check bytes for each subset of data bytes can be used to locate and correct any one data byte in error in the subset. However, the check bytes of all three subsets taken together can be used to locate and correct an error spanning a series of adjacent data bytes including one data byte from each subset.

POORU HOTSUJISU
WAANAA JIYOSEFU SHIYUUBURU
POORU RII SHIEIFUAA

JP6625079A

January 23, 1980

May 30, 1979

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IBM

G06F11/10; G06F12/16; H03M13/00; H03M13/13; H03M13/27; (IPC1-7): G06F11/10; G11C29/00; H04L1/10

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