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Patent Searching and Data


Title:
ERROR CORRECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH0294838
Kind Code:
A
Abstract:

PURPOSE: To send a syndrome to a terminal station without increasing redundancy by providing an error pulse generating circuit generating an error pulse able to be corrected in an output of an error correction coding circuit when a code error is detected by an error correction decoding circuit.

CONSTITUTION: A redundant bit is added to a transmission signal at the sender side to apply error correction to an information signal. Then an error correction decoding circuit 101 applies error correction based on the redundant bit to send a decoded information signal 2. An error correction coding circuit 102 inputs the information signal 2 and adds a redundant bit required for the error correction newly. Then a coded information signal 3 is sent to an error pulse generating circuit 3. If any error is generated in the transmission signal in the error correction decoding circuit 103, an error detection signal 4 is inputted to the error pulse generating circuit 3. Thus, the error pulse generating circuit 103 generates an error pulse at an optional position in the information signal 2 to send an information signal 5.


Inventors:
WATANABE MASAYOSHI
Application Number:
JP24422288A
Publication Date:
April 05, 1990
Filing Date:
September 30, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L1/00; (IPC1-7): H04L1/00
Attorney, Agent or Firm:
Kihei Watanabe