PURPOSE: To obtain an error correcting circuit of a small scale that has a high processing speed by connecting in series plural arithmetic units containing the multiplication circuits of parallel Galois fields, the addition circuits and plural registers respectively via buses.

CONSTITUTION: Plural units 1 are connected in series to each other via buses 2 and also connected to a common data bus 3. A controller 5 is connected to the bus 3 and then to each unit 1 via a control bus 4 and a '0' detecting signal line 6. Each unit 1 contains a multiplication circuit, an addition circuit, a multiplexer, a tristate gate, a control register, a register file and a 0-detecting circuit. In such a constitution, an Euclid dividing method is applied to decode a BCH code and an error is corrected by carrying out successively those steps, that is, the calculation of a syndrome, the draw-out of an error position polynomial, the draw-out of an error position, the calculation of an error pattern, and the correction of errors. In such a way, the processing speed is increased by several 10 times as high as that of a system which contains just a single pair of an adder and a multiplier.