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Title:
ERROR CORRECTION SYSTEM
Document Type and Number:
Japanese Patent JPS5520078
Kind Code:
A
Abstract:

PURPOSE: To ensure the transmission of the correct data regardless of the fault occurring at the data transmission circuit by sending the data to neutralize the error to the transmission side and then demodulating the data in case some error of the data transmission circuit is detected at the reception side.

CONSTITUTION: The data of transmission data register 11 is sent to data transmission circuit 13 via data conversion circuit 12 and demodulated at data demodulator circuit 14. This data is supplied also to error detection circuit 16. And if some error is detected, retransfer request circuit 17 is driven to send out the retransfer request through line 18 as well as to indicate circuit 14 to demodulate the neutralized data to the original data. Control circuit 19, when receiving the request through line 18, gives control to circuit 12 so that the neutralized data such as the data which transferred each bit may be transmitted. The neutralized data is received at circuit 14 to be converted and demodulated to the original data. Thus the error correction is ensured even though circuit 13 may be have the fixed fault.


Inventors:
Torii, Yoshiharu
Application Number:
JP1978000093866
Publication Date:
February 13, 1980
Filing Date:
July 31, 1978
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L1/16; H04L1/18; (IPC1-7): H04L1/16



 
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