To provide an error detection circuit suitable for detecting an error in a signal inputted in an input target such as memory.
An integrated circuit 1 includes error detection circuits 2A-2C and a memory circuit. The error detection circuits 2A-2C include latch circuits 21A0-21An for retaining the state of input signals IN0-INn at a rising edge of a clock signal CK and outputting first signals IN_A0-IN_An indicating the retained state, a delay circuit 20A for delaying the clock signal CK by delayed time t1, latch circuits 21B0-21Bn for retaining the state of the input signals IN0-INn at a rising edge of a delayed clock signal CK_A and outputting second signals IN_B0-IN_Bn indicating the retained state, and comparison circuits 24_0-24_n for comparing and determining whether the first signals IN_A0-IN_An and the second signals IN_B0-IN_Bn are identical and for outputting third signals COMP0-COMPn indicating determination results.
KATSUKI YOSUKE
Osamu Suzawa
Kazuhiko Miyasaka
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