Title:
ERROR DETECTION CODE GENERATOR AND ERROR DETECTOR
Document Type and Number:
Japanese Patent JP2018029227
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To make the number of bits to be added for detecting an error smaller than that of the ECC system.SOLUTION: An extraction section 22 compares the current number of bits of a parity generated by a parity generation section 21 and each bit of a control system signal 2a with the previous value and outputs the number of changed bits. A coding section 23 codes the number of changed bits from 4 bits to 3 bits and generates the primary overhead bits #0 to #2. A compression section 24 compresses the parity and the 3-bit primary overhead bits #0 to #2 and generates 2-bit transmission overhead bits #0 and #1.SELECTED DRAWING: Figure 1
Inventors:
TAKEHARA MASARU
Application Number:
JP2016159239A
Publication Date:
February 22, 2018
Filing Date:
August 15, 2016
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03M13/09; G06F3/00; G06F13/00; H04L1/00
Attorney, Agent or Firm:
Sakai International Patent Office
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