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Title:
ERROR DETECTION MECHANISM OF MICROPROGRAM SYSTEM
Document Type and Number:
Japanese Patent JPH05189256
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability of an error detection circuit and to improve the reliability of a system by verifying the operation of the error detection circuit.

CONSTITUTION: The error detection circuit 11 detecting the significance of the micro code in a microprogram executed by a control circuit executing a processing which the microprogram shows is provided with a flip flop 9 having the function of a set state instructing the occurrence of the error and that of a reset state releasing the set state, an error interruption generation means 19 inverting the parity bit of the micro code of the microprogram stored in the memory 13 by setting the flip flop 9 in the set state and generating interruption and an abnormality discrimination means discriminating the presence or absence of the abnormality of the operation of the error detection circuit 11 by the error status of the error detection circuit 11 when the error interruption generation means 19 generates interruption.


Inventors:
TSUTSUI NORIHIRO
Application Number:
JP390892A
Publication Date:
July 30, 1993
Filing Date:
January 13, 1992
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA COMPUTER ENG
International Classes:
G06F11/08; G06F11/22; G06F12/16; (IPC1-7): G06F11/08; G06F11/22; G06F12/16
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)



 
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