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Title:
ERROR DETECTION SYSTEM
Document Type and Number:
Japanese Patent JPS5260539
Kind Code:
A
Abstract:

PURPOSE: When information which has been set to the shift register is to be transferred to the duffer memory, proper detection is made for the error in the contents of the information set to the register.


Inventors:
Narita, Tokio
Maeda, Takeshi
Application Number:
JP1975000136598
Publication Date:
May 19, 1977
Filing Date:
November 13, 1975
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/10; G06F12/16; G06F13/00; G11B20/18; H03M13/00; (IPC1-7): G06F11/10; G06F13/00; G06F13/04; H04L1/10
Domestic Patent References:
JP46034455A