PURPOSE: To attain ease of test program forming and to simplify debugging by counting the number of times of generation of an error signal from an error signal generating circuit by a counter circuit to generate the error signal by a designated number of times.

CONSTITUTION: A data is fed to an AND circuit 16 via a decoder 12 from an error modulation register 11 to which error signal forming information is set by a command from a CPU, the circuit 16 ANDs an output from counter circuit 17 and the result is fed to an exclusive EOR 13. Further, a correction data corrected from an error detection circuit 3 is inputted to the EOR 13 and is written in a memory unit 1 from a memory write data register 15. Then the number of times of generation of error from an error generation circuit is counted by a counter circuit 17, an error signal is outputted from the circuit 16 for the designated number of times from the register 11 to attain ease of test program forming thereby simplifying debugging.