ESD PROTECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Title:

ESD PROTECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Document Type and Number:

Japanese Patent JP2002231886

Kind Code:

A

Abstract:

To provide an ESD protection circuit capable of suppressing an unnecessary current.

A P-channel MOS transistor PT1 is connected between a power line L1 and a power line L2. A P-channel MOS transistor PT2 is connected between the power line L1 and a gate of the P-channel MOS transistor PT1 and a voltage of the power line L2 is applied to the gate. A P-channel MOS transistor PT3 is connected between the gate of the P-channel MOS transistor PT1 and the power line L2 and a voltage of the power line L1 is applied to the gate. Substrates of P-channel MOS transistors PT1-PT3 are connected to the gate of the P-channel MOS transistor PT1. In this ESD protection circuit, all current path between the power line L1 and the power line L2 are shut off in any cases.

Inventors:

ARAI KATSUYA
KAGAMI TOSHIHIRO

Application Number:

JP2001023443A

Publication Date:

August 16, 2002

Filing Date:

January 31, 2001

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC IND CO LTD

International Classes:

H01L27/04; H01L21/822; (IPC1-7): H01L27/04; H01L21/822

Attorney, Agent or Firm:

Hiroshi Maeda (7 outside)

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