Title:
EVALUATING CIRCUIT FOR DIGITAL REVOLUTION SPEED TRANSMITTER
Document Type and Number:
Japanese Patent JPS57182174
Kind Code:
A
Abstract:
An evaluation circuit for receiving the output signals from a tachometer, the output signal consisting of first and second speed-proportional pulse trains which are phase-shifted with respect to one another in response to the direction of rotation. The evaluation circuit converts the phase-shifted pulse trains into a speed-proportional pulse train having a frequency which is four times that of the first and second pulse trains, and into a separate sign signal indicative of the direction of rotation. The first and second pulse trains are conducted to respective first and second signal memories which are controlled by a clock signal. In one embodiment, four possible states for the combined first and second pulse trains are assigned respective designating numbers. The count in a bidirectional counter is caused to follow changes in the designating numbers, the bidirectional counter counting pulses from the clock signal until such coincidence is achieved. The pulses so counted represent the desired speed-proportional pulse train. The present evaluation circuit operates to produce correct speed-proportional and direction-indicating signals even where the pulses of the first and second pulse trains are in phase with one another.
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Inventors:
URUFU KURAUSEN
Application Number:
JP5718882A
Publication Date:
November 09, 1982
Filing Date:
April 06, 1982
Export Citation:
Assignee:
SIEMENS AG
International Classes:
G01P3/489; G01P13/04; H02P29/00; G01P3/44; H03K21/02; (IPC1-7): G01P3/489; G01P13/04