To reduce the scale of a circuit for measuring a signal of a circuit to be evaluated, and the scale of the circuit for transferring measurement results.
In a counting section, signals to be evaluated 8, 9 of a circuit to be evaluated 2 are measured by measurement circuits 6, 7, and the measurement results are stored in an RAM 10. In an evaluation section that is longer than the counting section, the measurement results in the last counting section are read from the RAM 10. An adder 13 adds the measurement results of the latest counting section that are transferred from the measurement circuits 6, 7 to the measurement results of the previous counting section, which are read from the RAM 10. The addition results are written back to the original location of the RAM 10, thereby storing a cumulative addition value of the measurement results of the signals to be evaluated 8, 9 in the evaluation section in the RAM 10.
NIITSUMA JUNICHI
FUJIMOTO HIROAKI
FUJITA TAKASHI
JP2007102337A | 2007-04-19 | |||
JP2006285835A | 2006-10-19 | |||
JP2002288257A | 2002-10-04 | |||
JPH06162668A | 1994-06-10 | |||
JP2010038786A | 2010-02-18 | |||
JPH06162668A | 1994-06-10 | |||
JP2007293871A | 2007-11-08 | |||
JP2008209201A | 2008-09-11 | |||
JP2000242267A | 2000-09-08 | |||
JPH04313066A | 1992-11-05 |
Next Patent: IMAGE FORMING APPARATUS, CONTROL METHOD THEREFOR, AND PROGRAM