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Title:
EVALUATION METHOD AND DEVICE
Document Type and Number:
Japanese Patent JP2010182241
Kind Code:
A
Abstract:

To reduce the scale of a circuit for measuring a signal of a circuit to be evaluated, and the scale of the circuit for transferring measurement results.

In a counting section, signals to be evaluated 8, 9 of a circuit to be evaluated 2 are measured by measurement circuits 6, 7, and the measurement results are stored in an RAM 10. In an evaluation section that is longer than the counting section, the measurement results in the last counting section are read from the RAM 10. An adder 13 adds the measurement results of the latest counting section that are transferred from the measurement circuits 6, 7 to the measurement results of the previous counting section, which are read from the RAM 10. The addition results are written back to the original location of the RAM 10, thereby storing a cumulative addition value of the measurement results of the signals to be evaluated 8, 9 in the evaluation section in the RAM 10.


Inventors:
SASAKI TAKAYUKI
NIITSUMA JUNICHI
FUJIMOTO HIROAKI
FUJITA TAKASHI
Application Number:
JP2009027338A
Publication Date:
August 19, 2010
Filing Date:
February 09, 2009
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R31/28; G06F17/50
Domestic Patent References:
JP2007102337A2007-04-19
JP2006285835A2006-10-19
JP2002288257A2002-10-04
JPH06162668A1994-06-10
JP2010038786A2010-02-18
JPH06162668A1994-06-10
JP2007293871A2007-11-08
JP2008209201A2008-09-11
JP2000242267A2000-09-08
JPH04313066A1992-11-05
Attorney, Agent or Firm:
Akinori Sakai