PURPOSE: To evaluate an overlay accuracy and a dimension accuracy in a short time by locating a first verification pattern on each side of both arms of a second verification pattern for checking the state between the first and second verification patterns, conducting or nonconducting, and for measuring a resistance value of the second verification pattern.

CONSTITUTION: In the case that an overlay error between an actual basic pattern and a desired mask pattern is within the tolerance, the space between an arm 9a of a second verification pattern 9 and each of first verification patterns 8a and 8b is in the nonconducting state since one arm 9a of the second verification pattern 9 is located between the first verification patterns 8a and 8b. It is checked if the state of the spaces between the arm 9a of the second verification pattern 9 and each of the first verification patterns 8a and 8b and between the other arm 9b of the second verification pattern 9 and each of the other first verification patterns 8c and 8d are conducting or nonconducting. In the case that every space proves to be in the nonconducting state after the check, it is estimated that the overlay error between the actual basic pattern and the desired mask pattern is within the tolerance. In the case that any one space proves to be in the conducting state, it is estimated that the overlay error exceeds the tolerance. In this case, the direction of the overlay deviation can be specified by knowing which verification pattern is in the conducting state.