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Patent Searching and Data


Title:
EWS FOR DESIGNING LSI
Document Type and Number:
Japanese Patent JPH04255073
Kind Code:
A
Abstract:

PURPOSE: To make it unnecessary to set up texts by a manual and to improve a convergence property by executing arrangement, wiring and manual correction in a layout design, inputting the correspondence of external terminals to circuit diagram data and then executing layout verification and mask data formation.

CONSTITUTION: An arranging/wiring tool 8 executes arrangement/wiring based upon circuit diagram information stored in a circuit diagram editer 7. A layout editor 9 edits layout data and an electron beam output conversion tool 10 converts the edited data. A layout verification tool 12 verifys the layout based upon the outputs of the editor 7, the tool 8 and the editor 9. Namely the layout design is executed in the order of arrangement, wiring, correction, external terminal correspondence, verification, and decision. Consequently angle attributes can be added to the external terminal symbols of the circuit diagram data and the pad cells of the layout data.


Inventors:
SAKATA TAKESHI
Application Number:
JP1465391A
Publication Date:
September 10, 1992
Filing Date:
February 06, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Shin Uchihara