To solve difficulties and defects which are related to error correction by simultaneously storing data scramble-released in an EDC decoder and a storage area.

Four signals are read from a ring buffer DRAM 180 in a starting scramble release processing, and the signals are read into an EDC decoder 730 without undergoing scramble release. A signal output activates the code of a scramble releasing device LFSR circuit 720 from a state machine and an exclusive-OR XOR circuit is activated and executes an exclusive OR operation between a DESCR pattern signal and a BMD output signal. The output signal is inputted simultaneously to the EDC decoder LFSR circuit 730 and the DRAM 180. As a result, the DRAM 180 does not have to write data on the DRAM 180 any more after the decoder 730 has restored all the data. Then after all of the data have been sent, the scramble release processing is finished.