Title:
べき乗剰余演算器
Document Type and Number:
Japanese Patent JP4360792
Kind Code:
B2
Abstract:
A power-residue calculating unit includes a K register connected to a first internal bus for once storing an intermediate calculation result to be discarded when a power-residue calculation is executed in accordance with a binary method. Therefore even when data to be discarded appears during the calculation, a write into K register is performed, so that current in a write operation flows thereby improving immunity against Power Analysis.
Inventors:
Atsushi Yamaguchi
Application Number:
JP2002286182A
Publication Date:
November 11, 2009
Filing Date:
September 30, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G09C1/00; G06F7/72; G06F21/75; G06F21/86
Domestic Patent References:
| JP2001266103A | ||||
| JP2937982B2 | ||||
| JP11212456A | ||||
| JP2001195555A | ||||
| JP2002258743A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai