Title:
拡張分解能位相測定
Document Type and Number:
Japanese Patent JP4317923
Kind Code:
B2
Abstract:
A circuit (10) for determining periods of and the phase relationship between waveform signals (28 and 30). A delay line (12) having a sample port (14), a set port (16), a reference port (18), and an output port (20) and further internally including a chain of delay elements (32) associated with latch elements (34) and an encoder (36). The delay line (12) receive a first signal (28) into the sample port (14), and via a switch (22) also into the set port (16). The encoder (36) then provides the period of the first signal (28) at the output port (20) of the delay line (12) in units of delay created by each delay element (32). A control unit (24) then operates the switch (22) to direct a second signal (30) into the set port (16) for comparison with the first signal (28) at the sample port (14), and values are obtained at the output port (20) relating edges of a cycle in the second signal (30) to edges of the first signal (28), from which period of the second signal (30) and the phase relationship between the signals (28 and 30) is calculated with an arithmetic unit (26).
Inventors:
Wang, Nianz
Tsai, Mau-Quay
Tsai, Mau-Quay
Application Number:
JP50727199A
Publication Date:
August 19, 2009
Filing Date:
June 29, 1998
Export Citation:
Assignee:
Seapress Semiconductor Corporation
International Classes:
G01B9/02; G01R25/00; G01R23/10; G01R25/08; H04N9/44; H04N9/89
Domestic Patent References:
| JP3109096U | ||||
| JP854481A | ||||
| JP8211165A | ||||
| JP8297177A |
Attorney, Agent or Firm:
Nobuyuki Iida
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