PURPOSE: To output a memory enable signal and to eliminate operation failure caused by the setting deficiently of a DIP switch by detecting a bus width in accordance with whether an address brought to access to a bus high enable signal is an odd number or an even number.

CONSTITUTION: When the data bus width of a body side is 16 bits, the memory is constituted so that a memory 104 and a memory 105 are placed on the odd numbered address side and the even numbered address side, respectively, the memory 104 is connected to a high-order data bus 103, and the memory 105 is connected to a low-order data bus 102. The access of an odd numbered side is controlled by a BHE signal, and the access of an even numbered side is controlled by the least significant bit AO of an address bus 101. When them main body side is an 8-bit bus, the data bus 103 does not exist, therefore, it is necessary that not only data of the odd numbered side but also data of the even numbered side are inputted/outputted by using the data bus 102. Therefore, the data of the data bus 102 and 103 are swapped by using a swapping circuit 106.