Title:
SIGNAL VARIATION ACCELERATION BUS DRIVING CIRCUIT
Document Type and Number:
Japanese Patent JP3144374
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a signal variation acceleration bus driving circuit which is easy to design and small in circuit scale.
SOLUTION: This circuit is equipped with a high-level driving means 1 and a low-level driving means 2 which output a data signal IN to a bus, a control means 4 which controls the output of the data signal IN to the bus by the high-level driving means 1 or low-level driving means 2 according to an enable signal EN, and a control means 4 which accelerates variation in the voltage level of the bus by controlling the high-level driving means 1 and low-level driving means 2 according to the enable signal EN and the states of the voltage levels of the bus before and after the voltage level of the bus varies.
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Inventors:
Masahiro Nomura
Application Number:
JP4142998A
Publication Date:
March 12, 2001
Filing Date:
February 06, 1998
Export Citation:
Assignee:
NEC
International Classes:
G06F3/00; G06F13/40; H03K19/017; (IPC1-7): G06F3/00
Domestic Patent References:
| JP8286792A |
Attorney, Agent or Firm:
Shigeru Noda