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Title:
FLASH MEMORY CELL ON SeOI HAVING SECOND CONTROL GATE EMBEDDED UNDER INSULATING LAYER
Document Type and Number:
Japanese Patent JP2011124552
Kind Code:
A
Abstract:

To provide a memory cell that improves complexity of design of a peripheral circuit and reliability of the cell.

There is provided a flash memory cell 1A consisting of an FET transistor with a floating gate 20 on a semiconductor on-insulator substrate comprising a thin film of semiconductor material separated from a base substrate 5 by an insulating BOX layer, the transistor having, in the thin film, a channel 4. The flash memory cell 1A comprises two control gates, a front control gate 22 being arranged above the floating gate 20 and separated therefrom by an inter-gate dielectric 23 and a back control gate 6 being arranged within the base substrate 5 directly under the insulating BOX layer so as to be separated from the channel 4 only by the insulating BOX layer, the two control gates 22;6 being designed to be used in combination to perform a cell writing operation.


Inventors:
MAZURE CARLOS
FERRANT RICHARD
Application Number:
JP2010245443A
Publication Date:
June 23, 2011
Filing Date:
November 01, 2010
Export Citation:
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Assignee:
SOI TEC SILICON ON INSULATOR TECHNOLOGIES
International Classes:
H01L21/8247; H01L21/8242; H01L27/108; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
JP2009076680A2009-04-09
JP2000174241A2000-06-23
JP2008140912A2008-06-19
JP2003068896A2003-03-07
JP2006156925A2006-06-15
JP2008084956A2008-04-10
JP2002353342A2002-12-06
JP2000260887A2000-09-22
JP2008004831A2008-01-10
JP2006156925A2006-06-15
Attorney, Agent or Firm:
Hirohito Katsunuma
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Masashi Yoshida



 
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