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Title:
FABRICATION OF INSULATED GATE FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH06177148
Kind Code:
A
Abstract:

PURPOSE: To enhance gate-drain (source) breakdown voltage by oxidizing a gate electrode to form an oxide film, removing the oxide film, implanting impurity ions using the gate electrode as a mask, thereby forming a lightly doped drain region and a source region.

CONSTITUTION: A polycrystalline semiconductor gate electrode 3 is formed with a predetermined width on a semiconductor substrate through a gate insulation layer 2 and the surface of the gate electrode 3 is then oxidized to form an oxide film of predetermined thickness. The oxide film 4 is then removed by etching to leave the gate electrode 3 of width L1 which is used as a mask in the implantation of impurity ions thus forming a lightly doped drain and source regions 5, 6 on the semiconductor substrate 1. This method allows formation of an LDDMOS transistor having channel length shorter than that attainable by photolithography for forming the gate electrode 3 while enhancing gate-drain (source) breakdown voltage.


Inventors:
NOGUCHI TAKASHI
Application Number:
JP32814592A
Publication Date:
June 24, 1994
Filing Date:
December 08, 1992
Export Citation:
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Assignee:
SONY CORP
International Classes:
H01L21/265; H01L21/266; H01L21/28; H01L21/336; H01L29/78; (IPC1-7): H01L21/336; H01L21/265; H01L21/266; H01L29/784
Attorney, Agent or Firm:
Hidekuma Matsukuma