FABRICATION OF SEMICONDUCTOR DEVICE WITH AIR GAP FOR ULTRA-LOW ELECTROSTATIC CAPACITANCE INTERCONNECTION

Japanese Patent JP2010147495

A

To provide a method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce dielectric capacitive coupling between electrical elements such as metal lines.

The method of forming an air gap or gaps within semiconductor structures includes the processes of: (i) using a norbornene-type polymer as a sacrificial material to occupy a closed interior space in a semiconductor structure; (ii) causing the sacrificial material to decompose into one or more gaseous decomposition products (preferably self-decomposition through a heat treatment); and (iii) removing at least one of the gaseous decomposition products through at least one of solid layers adjacent to the closed interior space.

COPYRIGHT: (C)2010,JPO&INPIT

KOHL PAUL A
ZHAO QIANG
ALLEN SUE ANN BIDSTRUP

JP2010025535A

July 01, 2010

February 08, 2010

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GOODRICH CO B F

C08F32/00; H01L21/768; H01L21/312; H01L21/56; H01L21/764; H01L23/29; H01L23/31; H01L23/522

JPH0883839A	1996-03-26
JPH0745701A	1995-02-14
JPH0463807A	1992-02-28
JPH0883839A	1996-03-26
JPH0745701A	1995-02-14
JPH0463807A	1992-02-28

JPN6009005313; 'Ｒｅｄｕｃｅｄ　Ｃａｐａｃｉｔａｎｃｅ　Ｉｎｔｅｒｃｏｎｎｅｃｔ　Ｓｙｓｔｅｍ　ｕｓｉｎｇ　Ｄｅｃｏｍｐｏｓｉｔｉｏｎ　ｏｆ　Ａｉｒ　Ｇａｐ　Ｆｉｌｌｅｒ　Ｍａｔｅｒｉａｌ' ＩＢＭ　Ｔｅｃｈｎｉｃａｌ　Ｄｉｓｃｌｏｓｕｒｅ　Ｂｕｌｌｅｔｉｎ Ｖｏｌ．３８，　Ｎｏ．３９, 199509, ｐｐ．１３７-１４０
JPN6009005313; 'Ｒｅｄｕｃｅｄ　Ｃａｐａｃｉｔａｎｃｅ　Ｉｎｔｅｒｃｏｎｎｅｃｔ　Ｓｙｓｔｅｍ　ｕｓｉｎｇ　Ｄｅｃｏｍｐｏｓｉｔｉｏｎ　ｏｆ　Ａｉｒ　Ｇａｐ　Ｆｉｌｌｅｒ　Ｍａｔｅｒｉａｌ' ＩＢＭ　Ｔｅｃｈｎｉｃａｌ　Ｄｉｓｃｌｏｓｕｒｅ　Ｂｕｌｌｅｔｉｎ Ｖｏｌ．３８，　Ｎｏ．３９, 199509, ｐｐ．１３７-１４０

Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita

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