Title:
FACE-DOWN MOUNTING STRUCTURE
Document Type and Number:
Japanese Patent JP3710292
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent thermal stress concentration caused by difference in the linear expansion coefficient during mounting in a flip-chip method and restrain generation of passivation crack, by covering a region including a step part of a protection insulation film overlapping with a wiring and a terminal on an IC board excepting a part of a metallic projection with a metallic film.
SOLUTION: An Al wiring 6 and an Al pad 8 under a bump 1 (material of Au) are provided on an IC board 5 formed of Si. The Al wiring 6 and the Al pad 8 are coated with a passivation film 10 excepting a mounting position of the bump 1. A step part such as marks 2a, 2b is formed in a surface of the passivation film 10 covering an end part of the Al wiring 6 which is an uppermost layer wiring of an IC, and the parts 2a, 2b are covered with an extension part of a barrier metal (such as a lamination structure of a Ti layer and a Pd layer). As a result, it is possible to prevent local thermal stress concentration during mounting and furthermore during a reliability test in a flip-chip method, thus restraining generation of passivation crack.
Inventors:
Mitsushi Kitani
Application Number:
JP19750498A
Publication Date:
October 26, 2005
Filing Date:
July 13, 1998
Export Citation:
Assignee:
Canon Inc
International Classes:
H01L23/12; H01L21/60; (IPC1-7): H01L21/60; H01L23/12
Domestic Patent References:
| JP52150965A | ||||
| JP4364743A | ||||
| JP8045990A | ||||
| JP3244140A | ||||
| JP56008850A |
Attorney, Agent or Firm:
Jyohei Yamashita
Previous Patent: RECORDING APPARATUS CONTROL METHOD THEREFOR AND MEMORY MEDIUM
Next Patent: VIBRATION ISOLATOR
Next Patent: VIBRATION ISOLATOR